1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor memory device intended to reduce access time and power consumption thereof.
2. Description of the Background Art
In order to reduce power consumption of a semiconductor device such as a semiconductor memory device, it is effective to reduce power supply voltage Vcc supplied to the semiconductor device. This is because internal resistance is constant and power consumption is proportional to the square of the power supply voltage Vcc. However, compatibility of the semiconductor device with a semiconductor memory device which operates with power supply voltage which has not been reduced as operating power supply voltage must be maintained. Therefore, an internal voltage down-converter for down-converting externally supplied power supply voltage (hereinafter simply referred to as power supply voltage) Vcc to produce internal power supply voltage (hereinafter simply referred to as internal power supply) Vint which is lower than the power supply voltage Vcc is generally provided inside the semiconductor memory device. The semiconductor memory device is made to operate by the internal power supply Vint produced by the internal voltage down-converter.
FIG. 15 is a schematic diagram showing a structure of a conventional internal voltage generating circuit. FIG. 15 shows, together with the circuit for generating internal power supply Vint, a structure of a portion for generating internal high voltage Vpp which is higher than the internal power supply Vint. The circuit portion for generating internal power supply Vint and internal high voltage Vpp is hereinafter referred to as an internal voltage generating circuit.
The internal voltage generating circuit in FIG. 15 includes a constant current source 202 for supplying constant current; a reference potential generating circuit 203 for receiving constant current Ir from constant current source 202, and generating a reference potential Vref at a fixed voltage level which does not depend on power supply voltage Vcc when the power supply voltage Vcc is in a prescribed range; an internal power supply generating circuit 204 for generating internal power supply Vint on an internal power supply node 204x according to the reference potential Vref; and an internal high voltage generating circuit 205 for receiving the reference potential Vref and generating internal high voltage Vpp by charge pumping operation. The voltage level of internal high voltage Vpp is determined by the voltage level of reference potential Vref.
Internal power supply generating circuit 204 includes a differential amplifier 204a for differentially amplifying internal power supply Vint on internal power supply node 204x and reference potential Vref; a drive transistor 204b constituted by a p channel MOS transistor (an insulated gate type field effect transistor) coupled between an external power supply node EV and internal power supply node 204x and having its gate receiving an output signal from the differential amplifier 204a; a differential amplifier 204c activated upon activation of a row address strobe signal RAS, for differentially amplifying internal power supply Vint on internal power supply node 204x and reference potential Vref; a drive transistor 204d constituted by a p channel MOS transistor coupled between external power supply node EV and internal power supply node 204x and having its gate receiving an output signal from the differential amplifier 204c; and a p channel MOS transistor 204e coupled between external power supply node EV and the gate of drive transistor 204d and having its gate receiving row address strobe signal RAS. Differential amplifier 204a always operates, and increases conductance of drive transistor 204b by outputting a signal at a low level and supplies current from external power supply node EV to internal power supply node 204x when internal power supply Vint is lower than reference potential Vref. Since differential amplifier 204a operates at all times, it is made to have a small current driving capability in order to reduce current consumption thereof.
Differential amplifier 204c operates when row address strobe signal RAS is active. When the row address strobe signal RAS is inactive, that is, the semiconductor memory device is on standby, differential amplifier 204c is in a non-operative state. Differential amplifier 204c is made to have a large current driving capability. When the row address strobe signal RAS is active and internal circuitry operates consuming internal power supply Vint, differential amplifier 204c quickly responds to drive the drive transistor 204d to supply relatively large current from external power supply node EV to internal power supply node 204x through drive transistor 204d. Thus, reduction in internal power supply Vint during operation of the internal circuitry is suppressed. MOS transistor 204e is rendered conductive when the row address strobe signal RAS is inactive (at an L level), and supplies power supply voltage Vcc applied to external power supply node EV to the gate of drive transistor 204d, whereby it is ensured that drive transistor 204d is kept off. Thus, a current flowing path through drive transistor 204d is cut off during standby.
FIG. 16 is a diagram showing a structure of differential amplifiers 204a and 204c shown in FIG. 15. In FIG. 16, differential amplifier 204a includes a p channel MOS transistor 204aa connected between external power supply node EV and an internal node 204ax; a p channel MOS transistor 204ab connected between external power supply node EV and an internal node 204ay; an n channel MOS transistor 204ac connected between internal node 204ax and an internal node 204az and having its gate receiving reference potential Vref; an n channel MOS transistor 204ad connected between internal node 204ay and internal node 204az and having its gate receiving internal power supply Vint; and an n channel MOS transistor 204ae connected between internal node 204az and a ground node and having its gate receiving constant voltage Vcs. The constant potential Vcs is applied from constant current source 202 shown in FIG. 15, and MOS transistor 204ae functions as a current source.
Voltage to be applied to the gate of drive transistor 204b is output from internal node 204ax. MOS transistors 204aa and 204ab constitute a current mirror circuit, and MOS transistors 204ac and 204ad constitute a comparison stage. In this differential amplifier 204a, the gate of transistor 204a receives constant potential Vcs, and the supplying current thereof is reduced. Therefore, driving current (current flowing from external power supply node EV to the ground node) of differential amplifier 204a is reduced.
Differential amplifier 204c includes a p channel MOS transistor 204ba connected between external power supply node EV and an internal node 204bx and having its gate connected to an internal node 204by; a p channel MOS transistor 204bb connected between external power supply node EV and internal node 204by and having its gate connected to internal node 204by; an n channel MOS transistor 204bc connected between internal node 204bx and an internal node 204bz and having its gate receiving reference potential Vref; an n channel MOS transistor 204bd connected between internal node 204by and internal node 204bz and having its gate receiving internal power supply Vint; and an n channel MOS transistor 204be connected between internal node 204bz and the ground node and having its gate receiving the row address strobe signal RAS. MOS transistors 204ba and 204bb constitute a current mirror circuit, and MOS transistors 204bc and 204bd constitute a comparison stage.
Row address strobe signal RAS applied to the gate of current source transistor 204be varies between internal power supply Vint and ground potential. Therefore, current source transistor 204be is turned on completely when being conductive, and conductance thereof is made sufficiently larger than that of current source transistor 204ae. Furthermore, current supplying capability (channel width) of transistors included in differential amplifier 204c is also made relatively superior to (larger than) that of transistors in differential amplifier 204a. When row address strobe signal RAS attains an H level, internal circuitry of the semiconductor memory device operates and internal power supply Vint is reduced, differential amplifier 204b operates at a high speed, reducing the voltage level applied to internal node 204bx. Thus, conductance of drive transistor 204d rapidly increases, compensating for the reduction in internal power supply Vint, so that internal power supply Vint is returned to the reference potential Vref level.
In the case of the structure of the internal voltage generating circuit shown in FIGS. 15 and 16, differential amplifier 204c having large driving capability operates when row address strobe signal RAS is active. Accordingly, power consumption of differential amplifier 204c is large, and reduction in current consumption and power consumption of the entire semiconductor memory device cannot be achieved.
FIG. 17 is a diagram showing another structure of a conventional internal voltage generating circuit. The internal voltage generating circuit shown in FIG. 17 operates with power supply voltage Vcc on an external power supply node EV as operating power supply voltage, and includes a charge pumping circuit 210 for generating an internal voltage on a node N1 by charge pumping operation, a drive transistor 226 constituted by an n channel MOS transistor connected between external power supply node EV and an internal power supply node IV and having its gate connected to node N1, and a p channel MOS transistor 227 connected between node N1 and a ground node and having its gate receiving reference potential Vref from a reference potential generating circuit 203.
Charge pumping circuit 210 includes three stages of inverters 219, 220 and 221 constituting a ring oscillator; an inverter 222 for inverting an output signal of inverter 221; a charge pumping capacitor C1 responsive to an output signal of inverter 222 for performing charge pumping operation to change potential of a node 210a; an n channel MOS transistor 224 connected between external power supply node EV and a node 210a; a charge pumping capacitor C2 responsive to an output signal of inverter 221 for performing charge pumping operation to change a gate potential of MOS transistor 224; a diode-connected n channel MOS transistor 223 connected between external power supply node EV and the gate of MOS transistor 224; and an n channel MOS transistor 225 connected between node 210a and internal node N1 and having its gate connected to internal node 210a. This MOS transistor 225 functions as a diode.
MOS transistor 223 functions as a diode, and clamps the gate potential of MOS transistor 224 to the voltage level of Vcc-Vth. Vth is threshold voltage of MOS transistor 224. Charge pumping capacitor C2 causes the gate potential of MOS transistor 224 to change between 2.cndot.Vcc-Vth and Vcc-Vth according to the charge pumping operation thereof. MOS transistor 224 transmits power supply voltage Vcc to node 210a when the gate potential thereof is 2.cndot.Vcc-Vth. Charge pumping capacitor C1 causes potential of internal node 210 to change between 2.cndot.Vcc and Vcc according to an output signal of inverter 222. Therefore, voltage of 2.cndot.Vcc-Vth is transmitted to node N1 through MOS transistor 225. MOS transistor 227 has threshold voltage Vthp, has its gate receiving reference potential Vref, and operates in a source follower mode. Accordingly, potential of node N1 is clamped to the voltage level of Vref+.vertline.Vthp.vertline..
Drive transistor 226 operates in a source follower mode, and keeps the potential difference between the gate (node N1) thereof and internal power supply node IV at the level of threshold voltage Vthn. Therefore, internal power supply Vint is Vref+.vertline.Vthp.vertline.-Vthn.
The circuit structure shown in FIG. 17 is not provided with a differential amplifier. However, charge pumping circuit 210 operates at all times, resulting in large power consumption thereof. In particular, if the difference between voltage of 2.cndot.Vcc-Vthn output from charge pumping circuit 210 and reference potential Vref is large, MOS transistor 227 conducts at all times and supplies current from node N1 to the ground node, and therefore, current is consumed unnecessarily.
In addition, drive transistor 226 operates in a source follower mode, and supplies current from external power supply node EV to internal power supply node IV according to the potential difference between the gate and the source thereof, that is, the potential difference between node N1 and internal power supply node IV. When internal circuitry operates and internal power supply Vint rapidly reduces, large current flows through drive transistor 226. Drive transistor 226 is constituted by an MOS transistor, and has a specific channel resistance determined by its gate potential. Therefore, if relatively large current flows therethrough, the potential level of internal power supply Vint is reduced by the channel resistance of drive transistor 226, and the operating power supply voltage level of the internal circuitry is accordingly decreased, resulting in reduction in operation speed of the internal circuits. Consequently, in this case, the internal circuitry cannot operate stably at a high speed, and high speed access cannot be realized.
FIG. 18 is a diagram showing a structure of a data input/output (I/O) circuit of a semiconductor memory device. FIG. 18 shows a structure of a data I/O portion for 1 bit. In FIG. 18, a data output portion of the data I/O circuit includes an inverter 234 for inverting internal read data R; 2-input NAND circuits 237 and 238 activated in response to a data read instruction signal .phi.O, for inverting internal read data R and output data of inverter 234 to transmit those inverted data to internal nodes Na1 and Na2, respectively; an inverter 235 for inverting a data signal on a node Na1; a capacitor 247 responsive to an output signal of inverter 235 for carrying out charge pumping operation to transmit charges to a node Na3; a diode-connected n channel MOS transistor 240 connected between an internal power supply node IV and node Na3; an n channel MOS transistor 243 connected between external power supply node EV and a data I/O terminal Na4; an n channel MOS transistor 241 connected between the gate of MOS transistor 243 and a ground node and having its gate connected to node Na1; and a p channel MOS transistor 246 connected between node Na3 and the gate of MOS transistor 243 and having its gate connected to node Na1. MOS transistor 243 transmits power supply voltage Vcc on external power supply node EV to data I/O node Na4 when it is rendered conductive.
The data output portion further includes an n channel MOS transistor 244 connected between data I/O node Na4 and the ground node; a p channel MOS transistor 245 connected between internal power supply node IV and the gate of MOS transistor 244 and having its gate connected to node Na2; and an n channel MOS transistor 242 connected between the gate of MOS transistor 244 and the ground node and having its gate connected to node Na2.
A data write portion of the data I/O circuit includes an NAND circuit 239 for receiving a data write instruction signal .phi.I and write data on data I/O node Na4, an inverter circuit 236 for inverting an output signal of NAND circuit 239 to produce internal write data W. Operation will now be described briefly.
First, description of data read operation will be given. When a data read instruction signal .phi.O is inactive at an L level, a potential level on nodes Na1 and Na2 is an H level (an internal power supply Vint level). In this condition, node Na3 is held, by MOS transistor 240, at a voltage level lower than internal power supply Vint by threshold voltage thereof. Therefore, MOS transistor 246 is made turned off, while MOS transistor 241 is made turned on. In addition, MOS transistor 245 is off, while MOS transistor 242 is on. Thus, MOS transistors 243 and 244 of the output portion have respective gate potentials at the ground potential level and are made turn off, and data output node Na4 is forced to be in an output high impedance state.
If the data read instruction signal .phi.O attains an H level, NAND circuits 237 and 238 are enabled. Assuming that internal read data R is now at an H level, potential of node Na1 falls to an L level and an output of inverter 235 rises to an H level. In response to the rise of the output signal of inverter 235, potential on node Na3 rises to the level of 2.cndot.Vcc-Vth by the function of charge pumping capacitor 247. Thus, the potential on node Na3 is transmitted to the gate of MOS transistor 243 through MOS transistor 246. At this time, since MOS transistor 241 is off, gate potential of MOS transistor 243 is made at the level of 2.cndot.Vcc-Vthn, and the MOS transistor transmits voltage at the Vcc level to data I/O node Na4. At this time, internal node Na2 is at an H level and MOS transistor 244 is off.
When internal read data R is at an L level, potential level on node Na1 is an H level and potential level on internal node Na2 is an L level. In this condition, MOS transistors 246 and 243 are made turned off, while MOS transistor 241 is made turned on (this is the same condition as that in the case where the signal .phi.O is at an L level). On the other hand, MOS transistor 245 is turned on, while MOS transistor 242 is turned off, and gate potential of MOS transistor 244 is set at the internal power supply Vint level. Thus, MOS transistor 244 is turned on, and potential on data I/O node Na4 is discharged to the ground potential level.
In data write operation, write instruction signal .phi.I is activated at an H level. Thus, NAND circuit 239 and inverter 236 as a whole function as a buffer, and buffer write data applied to data I/O node Na4 to produce internal write data W.
In the structure of the data I/O circuit shown in FIG. 18, only the last data output stage is connected to the external power supply node, and other components operate with internal power supply Vint as operating power supply voltage. Interface between a memory and an external device can be achieved by outputting a signal, which swings between the external power supply voltage Vcc level and the ground voltage level, to data I/O node Na4.
However, internal power supply Vint is applied to the gate of MOS transistor 244. The gate potential of MOS transistor 244 is a potential level lower than an H level of data I/O node Na4, and conductance of MOS transistor 244 is reduced, so that data I/O node Na4 cannot be discharged at a high speed. If a channel width of MOS transistor 244 is increased in order to achieve large current driving capability thereof, data I/O node Na4 is accompanied with junction capacitance (substrate-drain capacitance and drain-gate capacitance) of MOS transistor 244 as parasitic capacitance. Therefore, parasitic capacitance of data I/O node Na4 increases, and thus cannot satisfy the capacitance value of, for example, 7pF at data I/O node Na4 determined by the specification value, so that quick charge/discharge of data I/O node Na4 cannot be achieved. In particular, data I/O node Na4 is also used for writing of data, and an external device cannot charge/discharge data I/O node Na4 quickly if this parasitic capacitance increases, so that the data writing speed is accordingly reduced. Consequently, if internal power supply Vint is reduced, data cannot be input/output at a high speed, resulting in difficulty in implementation of a semiconductor memory device which operates at a high speed.